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Global Mixed-mode Technology Inc.
G1432
2W Stereo Audio Amplifier
Features
Depop Circuitry Integrated Output Power at 1% THD+N, VDD=5V --1.8W/CH (typical) into a 4 Load --1.2W/CH (typical) into a 8 Load Maximum Output Power Clamping Circuitry Integrated Bridge-Tied Load (BTL) Stereo Input MUX Mute and Shutdown Control Available Surface-Mount Power Package 24-Pin TSSOP-P & 24-Pin QFN Available
General Description
The G1432 is a stereo audio power amplifier in 24pin TSSOP thermal pad package or 24pin QFN package. It can drive 1.8W continuous RMS power into 4 load per channel in Bridge-Tied Load (BTL) mode at 5V supply voltage. Its THD is smaller than 1% under the above operation condition. The G1432 can mute the output when Mute is activated. For the low current consumption applications, the SHDN mode is supported to disable the G1432 when it is idle. The current consumption can be further reduced to below 5A. The G1432 also supports two input paths, that means two different gain loops can be set in the same PCB and choosing either one by setting IN1 /IN2 pin. It enhances the hardware designing flexibility. The G1432 also supports an extra function -- the maximum output power clamping function to protect the speakers from burned-out.
Applications
Stereo Power Amplifiers for Notebooks or Desktop Computers Multimedia Monitors Stereo Power Amplifiers for Portable Audio Systems
Ordering Information
ORDER MARKING NUMBER
G1432F3U G1432Q5U G1432 G1432
TEMP. RANGE
-40C to +85C
PACKAGE (Pb free)
QFN4X4-24
-40C to +85C TSSOP-24 (FD)
Note: F3:TSSOP-24 (FD) Q5:QFN4X4-24 U: Tape & Reel
Pin Configuration
RBYPBASS
RIN1
RIN2
RVDD
G1432
GND/HS NC LOUT+ LIN1 LIN2 LBYPASS LVDD SHUTDOWN NC 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 GND/HS VOL ROUT+ RIN1 RIN2 RBYPASS RVDD GND IN1/IN2 ROUTMUTE GND/HS ROUT+ VOL GND/HS 19 20 21 22 23 24
17
16
15
14
GND
18
13 12 11
IN1/IN2
ROUTMUTE GND/HS GND/HS NC LOUT-
Thermal Pad
GND/HS NC LOUT+
Thermal Pad
10 9 8 7
LIN1
LBYPASS
GND/HS 12
Top View TSSOP-24 (FD)
Bottom View
G1432 QFN4X4-24
Note: Recommend connecting the Thermal Pad to the GND for excellent power dissipation.
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1
SHUTDOWN
LVDD
LIN2
NC
LOUT- 10 NC 11
2
5
1
3
4
6
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Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . .6V Input Voltage, VI . . . . . . . . . . . . . . . -0.3V to VDD+0.3V Operating Ambient Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to+150C Reflow Temperature (soldering, 10sec) . . . . . . 260C
Note:
(1) (2)
G1432
Power Dissipation (1) TSSOP-24 (FD) TA 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7W TA 70C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7W TA 85C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W Electrostatic Discharge, VESD Human body mode . . . . . . . . . . . . . . .-3000 to 3000V(2)
: Recommended PCB Layout. : Human body model : C = 100pF, R = 1500, 3 positive pulses plus 3 negative pulses
Electrical Characteristics
DC Electrical Characteristics, TA=+25C PARAMETER
Supply Current in Mute Mode DC Differential Output Voltage IDD in Shutdown
SYMBOL
IDD(MUTE) VO(DIFF) ISD
CONDITION
VDD =3.3V Stereo BTL VDD = 5V Stereo BTL VDD = 5V,Gain = 2 VDD = 5V
MIN
---------
TYP
7 8 5 2
MAX
13 16 50 5
UNIT
mA mV A
(AC Operation Characteristics, VDD = 5.0V, TA=+25C, RL = 4, unless otherwise noted) PARAMETER
Output power (each channel) see Note
SYMBOL
P(OUT)
CONDITION
THD = 1%, BTL, RL = 4 THD = 1%, BTL, RL = 8 THD = 10%, BTL, RL = 4 THD = 10%, BTL, RL = 8 PO = 1.6W, BTL, RL = 4 PO = 1W, BTL, RL = 8 VI = 1V, RL = 10K, G = 1 G = 1, THD =1% RL = 4, Open Load f = 120Hz f = 1kHz
MIN
---------------------------------
TYP
1.8 1.2 2 1.4 500 150 10 20 60 75 85 82 80 2 90 55
MAX
---------------------------------
UNIT
W
Total harmonic distortion plus noise Maximum output power bandwidth Phase margin Power supply ripple rejection Mute attenuation Channel-to-channel output separation
IN1 /IN2 input separation Input impedance Signal-to-noise ratio Output noise voltage
THD+N BOM PSRR
m% kHz dB dB dB dB M dB V (rms)
ZI Vn PO = 500mW, BTL Output noise voltage
Note :Output power is measured at the output terminals of the IC at 1kHz.
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(AC Operation Characteristics, VDD = 3.3V, TA=+25C, RL = 4, unless otherwise noted) PARAMETER
Output power (each channel) see Note
G1432
MIN
-----------------------------
SYMBOL
P(OUT)
CONDITION
THD = 1%, BTL, RL = 4 THD = 1%, BTL, RL = 8 THD = 10%, BTL, RL = 4 THD = 10%, BTL, RL = 8 PO = 0.7W, BTL, RL = 4 PO = 0.45W, BTL, RL = 8 VI = 1V, RL = 10K, G = 1 G = 1, THD 1% RL = 4, Open Load f = 120Hz f = 1kHz
TYP
0.8 0.5 1 0.6 270 100 10 20 60 75 85 80 80 2 90 55
MAX
---------------------------------
UNIT
W
Total harmonic distortion plus noise Maximum output power bandwidth Phase margin Power supply ripple rejection Mute attenuation Channel-to-channel output separation
IN1 /IN2 input separation
THD+N BOM PSRR
m% kHz dB dB dB dB M dB V (rms)
Input impedance Signal-to-noise ratio Output noise voltage
ZI PO = 500mW, BTL Vn Output noise voltage
-----
Note : Output power is measured at the output terminals of the IC at 1kHz.
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Typical Characteristics
Table of Graphs
FIGURE THD +N Total Harmonic Distortion Plus Noise Output Noise Voltage Supply Ripple Rejection Ratio Crosstalk Closed loop Response Supply Current vs Output Power vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Supply Voltage vs Supply Voltage vs Load Resistance vs Output Power 1,3,6,9,10,13,16 2,4,5,7,8,11,12,14,15 16,17 18,19 20,21 22,23 24 25 26 27,28
G1432
Vn
IDD
PO Output Power PD Power Dissipation
Total Harmonic Distortion Plus Noise vs Output Power
10 5 10 5
Total Harmonic Distortion Plus Noise vs Output Frequency
20kHz
2 1 0.5 % 0.2 0.1 0 .05 2 1
Po=1.8W
1kHz
%
0.5
0.2 0.1
20 Hz
Po=1.5W
0 .02 0 .01 3m
VDD=5V RL=3 BTL
20m 5 0m 1 00m W 20 0m 500 m 1 2 3
0 .05
VDD=5V RL=3 BTL Av=-2V/V
0 .02 0 .01 20
5m
10 m
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
Figure 1
Figure 2
Total Harmonic Distortion Plus Noise vs Output Power
10 5 10 5
Total Harmonic Distortion Plus Noise vs Output Frequency
2 1 0.5 % 0.2 0.1 0 .05
20kHz
Av=-4V/V
2 1
Av=-2V/V
1kHz
%
0.5
0.2 0.1
20 Hz
0 .02 0 .01 3m
VDD=5V RL=4 BTL
20m 5 0m 1 00m W 20 0m 500 m 1 2 3
Av=-1V/V
0 .05
0 .02 0 .01 20
VDD=5V RL=4 BTL Po=1.5W
1k 2k 5k 10 k 20k
5m
10 m
50
10 0
2 00
5 00 Hz
Figure 3
Figure 4
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Total Harmonic Distortion Plus Noise vs Output Frequency
10 5 10
G1432
VDD=5V RL=8 BTL Av=-2V/V
Total Harmonic Distortion Plus Noise vs Output Power
5
2 1 0.5 % 0.2 0.1 0 .05
VDD=5V RL=4 BTL Av=-2V/V
Po=1.5W Po=0.25W
%
2 1 0.5
20kHz
0.2 0.1
1kHz
Po=0.75W
0 .05
0 .02 0 .01 20
0 .02 0 .01 3m
20Hz
5m 10m 20m 5 0m 1 00m W 20 0m 500 m 1 2 3
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
Figure 5
Figure 6
Total Harmonic Distortion Plus Noise vs Output Frequency
10 5 10
Total Harmonic Distortion Plus Noise vs Output Frequency
5
2 1 0.5 % 0.2 0.1 0 .05
VDD=5V RL=8 BTL Av=-2V/V Po=0.25W
Po=1W
2 1 0.5 % 0.2 0.1
VDD=5V RL=8 BTL Po=1W Av=-2V/V
Av=-4V/V
Po=0.5W
0 .05 0 .02 0 .01 20
0 .02 0 .01 20
Av=-1V/V
50 10 0 2 00 5 00 Hz 1k 2k 5k 10 k 20k
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
Figure 7
Figure 8
Total Harmonic Distortion Plus Noise vs Output Power
10 5 10 5
Total Harmonic Distortion Plus Noise vs Output Power
20kHz
2 1 0.5 % 0.2 0.1 0 .05 2 1
20kHz
1kHz
%
0.5
1kHz
0.2 0.1
0 .02 0 .01 1m
VDD=3.3V RL=3 BTL
2m 5m 1 0m
20Hz
0 .05
VDD=3.3V RL=4 BTL
20Hz
0 .02 0 .01 1m
20 m W
50 m
10 0m
2 00 m
500 m
1
2m
5m
1 0m
20 m W
50 m
10 0m
2 00 m
500 m
1
Figure 9
Figure 10
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Total Harmonic Distortion Plus Noise vs Output Frequency
10 5 10 5
G1432
Total Harmonic Distortion Plus Noise vs Output Frequency
2 1 0.5 % 0.2 0.1 0 .05
VDD=3.3V RL=4 BTL Po=0.65W
Av=-4V/V Av=-2V/V
2 1 0.5 % 0.2 0.1
VDD=3.3V RL=4 BTL Av=-2V/V
Po=0.7W
Po=0.1W Po=0.35W
Av=-1V/V
0 .05
0 .02 0 .01 20
0 .02 0 .01 20
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
Figure 11
Figure 12
Total Harmonic Distortion Plus Noise vs Output Power
10 5 10
Total Harmonic Distortion Plus Noise vs Output Frequency
5
2 1 0.5 % 0.2 0.1 0 .05
20kHz
VDD=3.3V RL=8 BTL
2 1 0.5
VDD=3.3V RL=8 BTL Po=0.4W Av=-2V/V
Av=-4V/V
1kHz
% 0.2 0.1 0 .05
20Hz
0 .02 0 .01 1m 0 .02 0 .01 20
Av=-1V/V
2m
5m
1 0m
20 m W
50 m
10 0m
2 00 m
500 m
1
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
Figure 13
Figure 14
Total Harmonic Distortion Plus Noise vs Output Frequency
10 5
Output Noise Voltage vs Frequency
100 u 90 u 80 u 70 u 60 u
2 1 0.5 % 0.2 0.1
VDD=3.3V RL=8 BTL Av=-2V/V
Po=0.4W
50 u 40 u V
BW=22Hz to 22kHz
30 u
Po=0.1W
A- Weighted Filter
20 u
0 .05
VDD=5V Po=0.25W RL=4
10 u 20
0 .02 0 .01 20
50
10 0
2 00
5 00 Hz
1k
2k
5k
10 k
20k
50
100
2 00
50 0 Hz
1k
2k
5k
10k
2 0k
Figure 15
Figure 16
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Output Noise Voltage vs Frequency
100u 90u 80u 70u 60u 50u 40u V +0 -10 -20 -30 -40
G1432
Supply Ripple Rejection Ratio vs Frequency
T
VDD=5V RL=4 CB=4.7F
BW=22Hz to 22kHz
d B
-50 -60 -70 -80
30u
A- Weighted Filter
20u
VDD=3.3V RL=4
10u 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
-90 -100 -110 -120 20
50
100
200
500 Hz
1k
2k
5k
1 0k
20k
Figure 17
Figure 18
Supply Ripple Rejection Ratio vs Frequency
+0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 20
Crosstalk vs Frequency
-20 -25
T
VDD=5V RL=4 CB=4.7F
-30 -35 -40 -45 -50 -55 d B -60 -65 -70 -75 -80 -85 -90 -95 -100 20
VDD=5V Po=1.5W RL=4 BTL
L to R
R to L
50 100 200 500 Hz 1k 2k 5k 10k 20k
50
100
20 0
500 Hz
1k
2k
5k
10k
20k
Figure 19
Figure 20
Crosstalk vs Frequency
-20 -25 -30 -35 -40 -45 -50 -55 d B -60 -65 -70 -75 -80 -85 -90 -95 -100 20
Closed Loop Response
VDD=3.3V Po=0.75W RL=4 BTL
L to R
R to L
50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 21
Figure 22
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G1432
Supply Current vs Supply Voltage
Closed Loop Response
10 9 8 Supply Current(mA) 7 6 5 4 3 2 1 0 3
Stereo BTL
Figure 23
4 5 Supply Voltage (V)
6
Figure 24
Output Power vs Supply Voltage
2.5 THD+N=1% BTL Each Channel RL=4 1.5 RL=3 1 RL=8 0.5 2 1.8 1.6 Po-Output Power(W) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3.5 4.5 Supply Voltage (V) 5.5 6.5 0 0
Output Power vs Load Resistance
2 Po-Output Power (W)
VDD=5V
THD+N=1% BTL Each Channel
VDD=3.3V
4
8
12
16
20
24
28
32
Load Resistance()
Figure 25
Figure 26
Power Dissipation vs Output Power
1.8 1.6 Power Dissipation(W) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 Po-Output Pow er(W) 2 2.5 RL=8 VDD=5V BTL Each Channel RL=4 RL=3 Power Dissipation(W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0
Power Dissipation vs Output Power
RL=3
RL=4 RL=8 VDD=3.3V BTL Each Channel
0.25
0.5 Output Pow er(W)
0.75
1
Figure 27
Figure 28
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Pin Description
PIN TSSOP
2,9,11 3 4
G1432
FUNCTION
QFN
6,8,23 24 1
NAME
GND/HS NC LOUT+ LIN1
I/O
NC O I
1,12,13,24 9,10,21,22
Ground connection for circuitry, directly connected to thermal pad. Embedded test mode pin, please keep it floating. Left channel + output in BTL mode Left channel IN1 input, selected when IN1 /IN2 pin is held low.
5 6 7 8 10 14 15 16 17 18 19 20 21 22 23
2 3 4 5 7 11 12 13 14 15 16 17 18 19 20
LIN2 LBYPASS LVDD SHUTDOWN LOUTMUTE ROUTIN1 /IN2
I I I O I O I
Left channel IN2 input, selected when IN1 /IN2 pin is held high. Connect to voltage divider for left channel internal mid-supply bias. Supply voltage input for left channel and for primary bias circuits. Shutdown mode control signal input, places entire IC in shutdown mode when held high, IDD < 5A. Left channel - output in BTL mode. Mode control signal input, hold low for activation, hold high for mute. Right channel - output in BTL mode MUX control input, hold high to select in2 inputs (5,20)/(2/17), hold low to select in1 inputs (4,21)/(1,18). Ground connection for circuitry. Supply voltage input for right channel. Connect to voltage divider for right channel internal mid-supply bias. Right channel in2 input, selected when IN1 /IN2 pin is held high. Right channel lin1 input, selected when IN1 /IN2 pin is held low. Right channel + output in BTL mode The output power can be clamped by setting a low bound voltage to this pin. The high bound voltage will be generated internally. The output voltage will be clamped between high/low bound voltages. Then the output power is limited. It is weakly pull-low internally, let this pin floating or tied to GND can deactivate this function. Recommend connecting the Thermal Pad to the GND for excellent power dissipation.
GND RVDD RBYPASS RIN2 RIN1 ROUT+ VOL
I I I O I
Thermal Pad
Thermal Pad
Recommended Minimum Footprint
TSSOP-24 (FD) QFN4X4-24
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Block Diagram
(TSSOP/QFN Pin No.)
G1432
20k
21/18 20/17
RIN1 RIN2 RIGHT MUX
_
ROUT+ ROUT-
22/19 15/12
19/16
RBYPASS
+ RVDD 18/15
14/11 8/5 23/20
MUTE SHUTDOWN VOL
BIAS CIRCUITS MODES CONTROL CIRCUITS
IN1/IN2
16/13
LVDD LBYPASS + 5/2 4/1 LIN2 LIN1 LEFT MUX _ LOUTLOUT+
7/4
6/3
10/7 3/24
20k
Parameter Measurement Information
14/11 8/5 23/20
MUTE SHUTDOWN VOL IN1/IN2 16/13
LVDD 6/3 CB 4.7F CI AC source RI 5/2 4/1 LIN2 LIN1 LEFT MUX LBYPASS
7/4 RL 4/8/32
+ _
LOUTLOUT+
10/7 3/24
RF
BTL Mode Test Circuit
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Application Circuits
(TSSOP-24)
G1432
GND/HS NC LOUT+
CIR RFL CFR AUDIO SOURCE RIR
1 2 3 4 5 6 19 8 9 10 11 12
24 23 22 21 20 7
GND/HS VOL ROUT+ RIN1
RIL CIL RFL AUDIO SOURCE CFL
LIN1 LIN2
RIN2 LVDD RVDD GND IN1/IN2 ROUTMUTE GND/HS
CSR
LBYPASS RBYPASS SHUTDOWN NC LOUTNC GND/HS
G1432
18 17 16 15 14 13
Logical Truth Table Mute
X Low Low High
IN1 /IN2
X Low High Low
Shutdown
High Low Low Low Low
Input
X L/R IN1 L/R IN2 L/R IN1
OUTPUT L/R Out+ L/R Out---Output Output Output Output ---Output Output -------
Mode
Shutdown (Mute) BTL BTL Mute Mute
High
High
L/R IN2
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Application Information
(TSSOP-24/QFN4X4-24 Pin No.) Input MUX Operation There are two input signal paths - IN1 & IN2. With the prompt setting, the G1432 allows the setting of different gains for different input sources. If setting the IN1 /IN2 pin low, the IN1 input source is selected. When setting the IN1 /IN2 pin high, the IN2 input source is chosen. Bridged-Tied Load Mode Operation The G1432 has two linear amplifiers to drive both ends of the speaker load in Bridged-Tied Load (BTL) mode operation. Figure A shows the BTL configuration. The differential driving to the speaker load means that when one side is slewing up, the other side is slewing down, and vice versa. This configuration in effect will double the voltage swing on the load as compared to a ground reference load. In BTL mode, the peak-to-peak voltage VO(PP) on the load will be two times than a ground reference configuration. The voltage on the load is doubled, this will also yield 4 times output power on the load at the same power supply rail and loading. Another benefit of using differential driving configuration is that BTL operation cancels the dc offsets, which eliminates the dc coupling capacitor that is needed to cancelled dc offsets in the ground reference configuration. Low-frequency performance is then limited only by the input network and speaker responses. Cost and PCB space can be minimized by eliminating the dc coupling capacitors.
VDD
G1432
MUTE and SHUTDOWN Mode Operations The G1432 implements the mute and shutdown mode operations to reduce supply current, IDD, to the absolute minimum level during nonuse periods for battery-power conservation. When the shutdown pin (pin 8/5) is pulled high, all linear amplifiers will be deactivated to mute the amplifier outputs. And the G1432 enters an extra low current consumption state, IDD is smaller than 5A. If pulling the mute pin (pin 14/11) high, it will force the activated linear amplifier to supply the VDD/2 dc voltage on the output & shutdown the second linear amplifiers to mute the AC performance. In the mute mode operation, the current consumption will be a smaller than BTL modes. Shutdown and Mute pins should never be left unconnected, this floating condition will cause the amplifier operations unpredictable. Maximum Power Clampping Function
The G1432 supports the maximum output power clamping function to avoid damaging the speaker when the amplifier output a power beyond the speaker tolerance. The Vol pin (pin 23/20) is weakly pull-low internally. If inputting a non-zero voltage (low boundary voltage) to the Vol pin, the G1432 will generate a high boundary voltage which the difference between the VDD/2 and the high boundary voltage is the same as the difference between the VDD/2 and the low boundary voltage. ( i.e. VOH - VDD/2 = VDD/2 - VOL ) Then the outputs of linear amplifiers will be effectively limited between the high/low boundary voltage, the maximum output power is clamped. By setting the voltage of Vol, the maximum output power can be well controlled. When the maximum power clamping function is not used, the Vol pin should be floated or tied to GND.
Vo(PP) RL 2xVo(PP) -Vo(PP)
VDD
Figure A
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Optimizing DEPOP Operation
G1432
VDD 100 k 50 k
Circuitry has been implemented in the G1432 to minimize the amount of popping heard at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker and making the differential voltage generated at the two ends of the speaker. To avoid the popping heard, the bypass capacitor should be chosen promptly, 1/(CBx100k) 1/(CI*(RI+RF)). Where 100k is the output impedance of the mid-rail generator, CB is the mid-rail bypass capacitor, CI is the input coupling capacitor, RI is the input impedance, RF is the gain setting impedance which is on the feedback path. CB is the most important capacitor. Besides it is used to reduce the popping, CB can also determine the rate at which the amplifier starts up during startup or recovery from shutdown mode. De-popping circuitry of the G1432 is shown on Figure B. The PNP transistor limits the voltage drop across the 50k by slewing the internal node slowly when power is applied. At start-up, the voltage at BYPASS capacitor is 0. The PNP is ON to pull the mid-point of the bias circuit down. So the capacitor sees a lower effective voltage, and thus the charging is slower. This appears as a linear ramp (while the PNP transistor is conducting), followed by the expected exponential ramp of an R-C circuit.
Bypass 100 k
Figure B
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Package Information
C
G1432
L
D 24 D1 E1 E
E2
1
Note 5
A2 A1 e b
A
TSSOP-24 (FD) Package
NOTE: 1. Package body sizes exclude mold flash protrusions or gate burrs 2. Tolerance 0.1mm unless otherwise specified 3. Coplanarity : 0.1mm 4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact. 5. Die pad exposure size is according to lead frame design. 6. Follow JEDEC MO-153
SYMBOLS
A A1 A2 b C D D1 E E1 E2 e L
MIN
----0.00 0.80 0.19 0.20 7.7 4.4 4.30 2.7 0.45 0
DIMENSION IN MM NOM
--------1.00 --------7.8 ----6.40 BSC 4.40 ----0.65 BSC 0.60 -----
MAX
1.20 0.15 1.05 0.30 ----7.9 4.9 4.50 3.2 0.75 8
MIN
----0.000 0.031 0.007 0.008 0.303 0.173 0.169 0.106 0.018 0
DIMENSION IN INCH NOM
--------0.039 --------0.307 ----0.252 BSC 0.173 ----0.026 BSC 0.024 -----
MAX
0.047 0.006 0.041 0.012 ----0.311 0.193 0.177 0.126 0.030 8
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G1432
D2 b Pin #1 Identification Chamfer 0.3 X 45
Pin 1 Dot By Marking
D L
e E E2
Top View
e1
A A2 A1
QFN4X4-24 Package
SYMBOL
A A1 A2 b D D2 E E2 e e1 L
MIN.
0.700 0.000 0.178 0.225 3.950 2.650 3.950 2.650
DIMENSION IN MM NOM.
--------0.203 0.250 4.000 2.700 4.000 2.700 0.500 BSC 2.500 REF 0.400
MAX.
1.000 0.050 0.228 0.275 4.050 2.750 4.050 2.750
MIN.
0.028 0.000 0.007 0.009 0.156 0.104 0.156 0.104
DIMENSION IN INCH NOM.
--------0.008 0.010 0.157 0.106 0.157 0.106 0.020 BSC 0.098 REF 0.016
MAX.
0.039 0.002 0.009 0.011 0.159 0.108 0.159 0.108
0.350
0.450
0.014
0.018
Taping Specification
PACKAGE
TSSOP-24 (FD) QFN4X4-24
Feed Direction Typical TSSOP Package Orientation Feed Direction Typical QFN Package Orientation
Q'TY/REEL
2,500 ea 3,000 ea
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
Ver: 1.1 Jun 21, 2006
TEL: 886-3-5788833 http://www.gmt.com.tw
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